Design Technology Productivity in the DSM Era

Future requirements for design technology are always uncertain due to changes in process technology, system implementation platforms, and applications markets. To correctly identify the design technology need, and to deliver this technology at the right time, the design technology community – commercial vendors, captive CAD organizations, and academic researchers – must focus on improving design technology time-to-market and quality-of-result. Put another way, we must address the well-known Design Productivity Gap by addressing the Design Technology Productivity Gap. The future of design technology is most uncertain in the physical implementation space, where many complexities must be managed without sacrificing system value or turnaround time. This talk will begin with examples of changes in methodology and design tool infrastructure needed to support future physical implementation. Then, recent initiatives in the MARCO Gigascale Silicon Research Center (GSRC) are described which support the design technology and designer communities in creating the right design technology when it is needed. 1 Background: DSM Challenges The litany of back-end DSM challenges is well-known. (1) Challenges of the small are induced by sub-50nm scaling, and bring to the forefront issues of current density and power, synchronization, manufacturing variability, high-frequency and coupling noise, and yield (manufacturing cost). (2) Challenges of the large are induced by > 10 transistor integration, and center on system complexity and cost (notably design costs along axes of resource, quality and time-to-market). (3) Challenges of the heterogeneous are induced by the encapsulation, reuse and integration of CMOS logic along with mixed-signal and RF, MEMS, and memory technologies. For background, we briefly sketch example challenges arising in design convergence and the designmanufacturing interface. Our purpose in presenting this small sampling of DSM challenges is to illustrate how future technical solutions will require integration across many different types of tools. Indeed, integration and cross-domain optimization are common themes for future design technologies. Example 1: Design Convergence. Design convergence is the convergence of logic, timing and spatial embedding; from a functional viewpoint, it represents the support of front-end signoff by a predictable back-end. Future technology regimes will entail global wires > 100x faster than local wires, single via stacks with > 12 ohms, over 80% of wire capacitance arising from coupling, and worst-case “Miller coupling factors” increasing from 2 to more than 9 as gates switch faster and wire pitch decreases. In such regimes, (static) signal integrity and timing signoff methodologies become problematic due to increased guardbanding. Moreover, front-end signoff of parasitic and performance estimates require predictability of distributed RLC interconnect topologies. Previous statistical prediction methods to decouple logic and physical syntheses (e.g., block-specific wireload models) suffer from increased iterations and non-convergence. Newer “RTL-to-GDSII” methodology variants achieve predictability in several ways. (1) Correct by construction methods assume a result, then enforce it. Examples include constant-delay (gain-based) logic synthesis, and the use of hard chip-level global routes to define global timing and pin assignments before block synthesis. Iterations are reduced at the cost of guardbanding. (2) Construct by correction methods acknowledge the Partially supported by the MARCO Gigascale Silicon Research Center. need to iterate, but architect tools to support this. Examples include unified logic and layout synthesis, or, unified analysis and synthesis (e.g., tying incremental extraction and static timing to incremental place and route). (3) Ignore by prevention methods apply “methodology” to make certain issues ignorable. Examples include (i) rules for repeater insertion, slew time control, and layer assignment to solve sizing and signal integrity issues [19, 9], (ii) rules for grounded shielding to improve inductance estimation [9], or (iii) “noise-free fabrics” [21]. These avenues to design convergence, while reasonable and viable, share several technical challenges. (1) RTL partitioning must create blocks that can be placed and budgeted well, and also must recognize and diagnose a “physically challenged” RTL. (2) Block “packing” mindsets must give way to more relevant “shaping” that integrates with wire planning and timing optimization to yield zero-whitespace, zero-overlap results [17]. (3) When block areas and timings are not yet fixed, global interconnect plans must support design changes smoothly. More generally, optimization under design changes or under incomplete design information becomes more critical [12, 18]. (4) The synthesis, place and route (SP&R) back end must be highly controllable and handle constraints well. For example, if a local routing resource has been used by a noise-sensitive global bus, the back end must work around this. (5) Since there is always a chicken-egg problem for top-down planning, estimators that drive initial synthesis and budgeting must always be improved (e.g., [6, 11]). The high-level observation is that future methodology variants require push-button back-end SP&R. Thus, the most interesting implication of “back-end design convergence” is that synthesis, place and route – along with such supporting technology as extraction and static timing analysis – become commoditized (just like delay calculation or Verilog simulation today). Moreover, individual point tools become less valuable as integration becomes the driving consideration. Example 2: Design-Manufacturing Interface. Future design technology must address both random and systematic variabilities, with the latter encompassing intrinsic layout-pattern dependent and exposuresystem dependent effects (iso-dense or lens aberration impacts on device and interconnect CDs) as well as dynamic effects (temperature, Vdd, etc.). Two examples come from use of aperture and phase in optical lithography to make sub-wavelength feature sizes. (1) Changing aperture to correct for line-end shortening, corner rounding, etc. implies more complicated mask shapes in the form of optical proximity correction (OPC). OPC affects data volumes and DRC, but more critically impacts mask writing and inspection costs. For example, future design technology must allow “function-aware” OPC that is applied only as needed (e.g., to features in critical paths which require better CD control). This entails passing performance analysis and functional intents from logic-layout synthesis to physical verification. Required flow integrations must span library creation, detailed routing and physical verification (e.g., so that an optical correction is not made independently by several tools, leading to an incorrect result). (2) Changing phase to improve contrast and resolution is achieved by phase-shifting masks (PSM) [22], which exploit destructive cancellation of diffraction to create more perfect contrasts between light and dark regions on the wafer. Since 1999, the ITRS has specified PSM as a required technology solution that enables Roadmap acceleration (cf. physical bottom gate length in logic, and transistor densities, in the 2000 ITRS ORTCs, Figure 1). With PSM, certain DRC-correct layouts cannot be manufactured, because legal assignment of (e.g., 0 and 180) phases in the mask is impossible [20]. Such phase conflicts must be addressed Figure 1: Roadmap acceleration, showing anticipated DRAM halfpitch and logic bottom gate length in the 2000 ITRS Update. by moving and/or widening some subset of layout features. To maintain back-end layout productivity as well as the layout reuse inherent in, e.g., standard-cell methodology, responsibility for PSM must be distributed across a highly-integrated toolset that spans library creation, full-custom layout support, technology migration, and standardcell place and route. Other facets of the design-manufacturing interface also present challenges to future design technology. For example, (3) pattern density variation causes dishing of inter-layer dielectrics in chemicalmechanical planarization. With copper interconnect, this is particularly troubling since copper is so soft; the 2000 ITRS therefore has copper dishing and thinning as a fundamental process parameter. At the device level, uneven layout density can result in contact overetch and uneven vapor deposition. The solution is to introduce extra dummy fill to make the process result more uniform. This must not only be driven by the best possible models of the manufacturing process, but flow issues abound: (i) dummy metal fill will change RC extraction results, and must be accounted for in the upstream timing verification before the layout goes to physical verification; and (ii) data volumes and design hierarchies must be maintained. Just as with OPC and PSM, dummy fill requires a complete, integrated, front-to-back solution. The design-manufacturing interface brings design technology much closer to the foundry and capital investment. Tight links with process development and the mask industry must be made, e.g., to transmit functional information to mask writing, inspection and verification, and cost models back up to the design tools. Traditional “physical verification” will become embedded all the way up to library creation, logic synthesis, and place-and-route. Unified, frontto-back solutions will win. The Challenge: Too Many Challenges. The above are are only a small sampling of the technical, integration, and cross-domain challenges that face future design technology. The key conclusion is that there are too many critical challenges for the design technology community to solve with its available resources. 2 The Design Technology Productivity Gap This section develops the concept and implications of the Design Technology Productivity Gap. We start with five observations. First, the famous Design Productivity Gap (Figure 2) states that the number of available raw transistors increases by 58%/year while the designer’s capability to design them grows by only 21%/year. Observation 1: The cost of designing a transistor increases exponentially relative to the cost of the raw transistor. Second, while the ITRS documents Silicon cost (at volume production, for particular classes of designs), it does not document Figure 2: Design Productivity Gap. Product cost (= Non-Recurring (NRE) cost + Silicon cost). We must ask: If design technology is not improving fast enough, then how costly will designs be in the future? Put another way, how many gates can one obtain for $1 or $10? Certainly, OPC and PSM increase the NRE component of system cost. A 25level mask set will cost around $1M in the 130nm process generation, which arrives this year. At the same time (according to SEMATECH figures), an average of only 500 wafers are processed with a given mask set. Changing reticle reduction factors (e.g., 5X or 6X on 6-inch or 7-inch glass), placing multiple designs on a single mask set, and improved yield learning will mitigate these costs. However, if we acknowledge the exponentially increasing cost of designed transistors, and the need to amortize $5B capital cost per foundry, there is only one possible conclusion. Observation 2: Only high-value, high-volume designs will be affordable in the future. Third, we may consider what is “easy” versus “hard” for design tools. Today, less effort is required to achieve a given return if we design at a higher level. For example, solving power problems is difficult with placement and wiresizing, easier with clock gating, and even easier by adding sleep mode to the system. This difference may be magnified in the future, as DSM physics become very complicated. Design productivity requires designers to design and hand off to implementation at higher and higher levels, but DSM physics forces the implementation platform to remain at a low level. Observation 3: There is a widening implementation gap, i.e., separation between where designers need to design, and the reliable (RTL-down) back end. Fourth, while long-term research – such as that within the MARCO GSRC – may eventually address the implementation gap, there is no currently available solution. (1) Making simpler designs (e.g., filling up transistors with memory and reused logic) is one obvious implication of any “productivity gap” between newor reused-logic productivity and available transistors: if designer resources are not expanded to fill the gap, then large chips must contain more “free” (memory) transistors. However, this does not create high-value designs. (2) Making the back-end implementation easier (e.g., with noise-free circuit fabrics [21]) or enabling easier block reuse in SOC (e.g., via communication-based design (“TCP/IP on chip”) [25]) improves productivity but harms density and performance. Again, high-value designs are not possible. Observation 4: There is no known solution to the implementation gap that does not compromise design quality and value. Works of W. Maly have given detailed analyses of cost contradictions inherent in the NTRS/ITRS, and of the need to temper Moore’s Law with cost realities. An example work is [23]. This implementation gap, noted by K. Keutzer and colleagues in the MARCO GSRC, has motivated several core research themes within the GSRC. STRJ (Japan Semiconductor Technology Roadmap) colleagues have performed one such analysis. Under current productivity growth rate assumptions, 94% of the die will be populated with memory in 2014 if design effort is to remain at current levels. Fifth, we recall the economic need for high-volume, high-value designs (“keeping the fabs full”). If high-value designs cannot be created quickly enough, then the semiconductor industry must attempt workarounds. For example, platform-based SOC design (cf. [10] and work of Keutzer, Malik, Sangiovanni-Vincentelli et al. in the MARCO GSRC) attempts to realize a handoff level between architecture and microarchitecture. In the platform-based approach, “front end” compilation of application down to architecture goes hand in hand with microarchitecture serving as the compiled abstraction of the silicon process. Where traditional structured-custom design creates a unique mapping of each microarchitecture to silicon (i.e., a unique chip with unique CAD), platform-based design allows compilation of entire application families (e.g., 3G wireless) down to a single platform. Such approaches, if successful, would be high value for the system house, but incompatible with traditional design technology and ASIC business models. On the other hand, platform-based approaches may be unsuccessful because they again leave quality and value on the table. Observation 5: If the “platform-based” design productivity workaround succeeds, it will be will at the cost of design technology’s inherent value. On the other hand, platform-based design can fail if it unacceptably compromises design value. Design productivity cannot be separated from design quality. Hence, there is no shortcut or workaround: we truly require design technology to deliver high-value silicon with low design cost. This brings us back to the Challenge above: Too many challenges, too few resources. Initiatives within the MARCO GSRC The Calibrating Achievable Design (C.A.D.) theme in the MARCO GSRC [4] identifies the Design Productivity Gap with the Design Technology Productivity Gap. Aspects of this gap include: Design technology lacks a clear industry-wide R&D agenda (e.g., a “roadmap”). There is a long time-to-market (up to 5-7 years to transfer leading-edge publications to production flows), which forces designers to battle today’s design problems using yesterday’s design technology. There are few means of assessing quality-of-result, e.g., it is difficult to evaluate the impact of new tools on the overall design process, and published descriptions are insufficient for replication or even comparison of algorithms. When R&D cannot identify, evaluate or reuse the design technology leading edge, research and innovation become stalled. Corresponding causes of the design technology gap include: Lack of roadmapping with respect to the ITRS and applications markets. Lack of “Foundation CAD-IP”: interoperable, reusable, commodity infrastructure upon which new design technology can be built. Relative over-resourcing of non-strategic, de facto commodity technology (e.g., GDSII or SPICE format readers/writers, delay calculators, netlist partitioners, etc.) – and a concomitant lack of maturity with respect to control and strategic-vs.-commodity distinctions. Lack of standard metrics and benchmarks for design technology. Notably, the platform-based approach faces challenges for very low-power, very highthroughput applications. For example, J. Rabaey and colleagues have documented well over 1000x quality differences (MOps/mW) between dedicated hardware and, e.g., embedded low-power StrongARM core. We believe that mature, coopetive (= competitive + cooperative) cultures and shared, open infrastructures that lead to improved specification, creation and delivery of design technology. To make this more concrete, we focus on (1) criteria that apply to any technology delivery, namely, time-to-market and quality-of-result (QOR), and on (2) three basic questions that pertain to the design technology life cycle. What will the design problem look like? What problems do we need to solve, by when? In other words, we must specify the required technology. How can we quickly develop the right design technology so that it is available at the right time (i.e., time-to-market)? In other words, once we know the right design problem, we must be able to quickly develop and deploy a solution. Did we really solve the problem (i.e., QOR)? Did the design process improve? In other words, we must be able to measure our progress. The remainder of this paper describes three initiatives whose goal is to enable the design technology community to answer these questions. 3 Technology Extrapolation What will the design problem look like? Leading-edge VLSI system design aggressively exploits new process technologies, circuit techniques, design methodologies and design tools. It is thus difficult to predict the envelope of achievable design – e.g., with respect to power, speed, area, manufacturing cost, etc. – for a given behavior or function, in a given (future) process technology. On the other hand, such technology extrapolation activity directly influences the evolution of future VLSI system architectures, design methodologies, and design tools. Via roadmapping efforts such as the International Technology Roadmap for Semiconductors (ITRS) [16], technology extrapolation also influences levels of investment in academic research, career choices for faculty and graduate students, as well as private-sector entrepreneurial activity. Highly influential technology extrapolation systems are due to Bakoglu and Meindl (SUSPENS) [29] and Sai-Halasz [28]. More recent efforts include GENESYS [27], RIPE [26] and BACPAC [30], along with Roadmap-related efforts [16] and innumerable internal projects throughout industry and academia. Typically, each system provides a plausible “cycle-time model” and estimates of die size and power dissipation, based on a small set of descriptors spanning device/interconnect technology through system architecture. We observe that (i) these systems are often incomparable, (ii) they are “hardcoded” (hence it is difficult to assess their quality and to explore changes through modeling choices), and (iii) their development has entailed a near-total duplication of effort. These observations motivate efforts toward an entirely new level of technology extrapolation capability. The GSRC Technology Extrapolation (GTX) system [5] has been developed with the goals of flexibility, quality and prevention of redundant effort in mind. GTX addresses these goals by providing an open, portable framework for specification and comparison of alternative modeling choices. A fundamental design decision in GTX is to separate model specifications from the derivation engine. This separation is achieved by a human-readable ASCII grammar. As domain-specific knowledge is represented independently of the derivation engine, it can be created and shared by multiple users. Additional extension mechanisms allow specialized prediction methods, technology data sets, and even optimization engines to be encapsulated and shared within GTX; this further reduces the amount of effort that is diverted from actual creation of best-possible prediction models. For example: Should EDA tools focus on support of dynamic logic synthesis at sub-1 volt supplies Should detailed routers be made PSM-aware? Should circuit design techniques address single-event upsets? Our claim is that in avoiding misguided development efforts, better focus and productivity of the design technology will be achieved. The GTX framework has prompted development of new SOI and bulk Si device models; models for global interconnect optimizations (incorporating repeater staggering and bus swizzling, shield insertion, etc.), global RLC interconnect delay, and coupling noise; yield and cost models for logic and DRAM; manufacturing variability models; etc. These models, along with studies of power dissipation, delay uncertainty, clock skew, etc. have been released in open-source form along with the GTX system itself. Other efforts have developed design-specific interconnect process optimizations that are based on new models of routability and layer assignment calibrated to industry place-and-route results. A long-term goal is for the (open source, multi-platform) GTX release to literally provide a “living roadmap” (including core portions of the ITRS, as feasible) that extrapolates manufacturing and design technologies and their implications in a transparent, self-consistent way.